1. Field of the Invention
The present invention relates to a method for forming a pad in a wafer with a three-dimensional stacking structure, and more particularly, to a method for forming a pad in a wafer with a three-dimensional stacking structure, in which a process for etching an Si substrate is not separately performed after a process for thinning the back side of a device wafer, vias are formed on the back sides of super contacts after forming dielectric layers, and a pad is formed on the back sides of the vias.
2. Description of the Related Art
A wafer stacking technology will be a key technology for a next-generation high-end semiconductor. In order to manufacture such a semiconductor, numerous companies conduct research and development.
One of important technologies for wafer stacking is a technology of forming a pad after bonding.
FIGS. 1a through 1c show a series of processes for forming a pad according to the conventional art.
FIG. 1a illustrates a cross-section when a process for thinning the back side of a device wafer is performed after bonding a handling wafer and the device wafer according to the conventional art.
Referring to FIG. 1a, in the conventional art, an Si substrate 110 has a thickness of approximately 3.5 μm by a back side thinning process.
FIG. 1b illustrates a cross-section after a process for etching an Si substrate and a process for depositing a dielectric material according to the conventional art.
Referring to FIG. 1b, in a first step, the thickness of the Si substrate 110 is reduced from 3.5 μm to 3 μm through etching. After the first step is completed, an SiO2 layer 121, an SiN layer 123 and an SiO2 layer 125 as dielectric materials are sequentially formed on the back side of the etched Si substrate 110 in a second step.
FIG. 1c illustrates a cross-section after a process for planarizing a dielectric layer and a process for forming a pad according to the conventional art.
Referring to FIG. 1c, in a first step, the SiO2 layer 125 is planarized through CMP (chemical mechanical polishing).
After the first step is completed, a pad 130 is formed by performing metal (Al) deposition, photolithography and etching which are generally known in the art.
The conventional method for forming a pad has problems as described below.
First, in the conventional art, after back side thinning of a device wafer 110b, the Si substrate 110 is separately etched as shown in FIG. 1b. Therefore, it is necessary to consider the final thickness of the Si substrate 110, and the imaging characteristics of an image sensor are likely to deteriorate due to damage to super contacts 120 or the surface of the Si substrate 110.
Second, since the number and the density of the super contacts 120 are small, dishing is likely to occur when planarizing the dielectric layer as shown in FIG. 1c. As a consequence, it is difficult to perform subsequent processes. Also, because target setting for the planarization of the dielectric layer is required, it is necessary to isolate the Si substrate 110 and the pad 130 from each other.